By Eric A. Vittoz (auth.), Rudy J. van de Plassche, Willy M. C. Sansen, Johan H. Huijsing (eds.)
The awareness of sign sampling and quantization at excessive pattern charges with low strength dissipation is a crucial objective in lots of purposes, includ ing moveable video units comparable to camcorders, own verbal exchange units reminiscent of instant LAN transceivers, within the learn channels of magnetic garage units utilizing electronic info detection, and so forth. This paper describes structure and circuit techniques for the layout of high-speed, low-power pipeline analog-to-digital converters in CMOS. the following the time period excessive pace is taken to suggest sampling charges above 1 Mhz. within the first part the dif ferent conversion strategies appropriate during this diversity of pattern premiums is dis stubborn. Following that the actual difficulties linked to energy minimization in video-rate pipeline ADCs is mentioned. those contain optimi zation of capacitor sizes, layout of low-voltage transmission gates, and opti mization of switched capacitor achieve blocks and operational amplifiers for minimal strength dissipation. to illustrate of the applying of those tech niques, the layout of a power-optimized lO-bit pipeline relief converter (ADC) that achieves =1. sixty seven mW in step with MS/s of sampling expense from 1 MS/s to twenty MS/s is defined. 2. thoughts for CMOS Video-Rate reduction Conversion Analog-to-digital conversion ideas might be labeled in lots of methods. One handy technique of evaluating thoughts is to check the variety of "analog clock cycles" required to supply one powerful output pattern of the sign being quantized.
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Additional info for Analog Circuit Design: Low-Power Low-Voltage, Integrated Filters and Smart Power
Thus. the tail-current of the actual active input pair has a value of 4lref The result is an approximately constant gm. In the transition regions of the current-switches the gm varies about 15%. as is shown in Fig. 17 . It should be noted that the offset voltage of rail-to-rail input stages changes 30 ~----r-----r-----~r------------r-----,--,-~VDD ~--~~----~----~~----------~----~----~V~ Fig. 16. Rail-to-rail input stage. The 3-times current mirrors control the gm' when the complementary input stage gradually switches from one input pair to the other.
The coupling of the class-AB circuit is so strong that one of the signal current-sources, lin] and lin2' will suffice to drive the output transistors. --"-------+--~ Qp ' - - - - - - - - - - ' - - - - ' - - - - i D VEE Fig. 20. Bipolar rail-to-rail output stage with resistive class-AB control. '-----'----'-----'---fJVEE Fig. 21. Bipolar rail-to-rail output stage with resistor coupledfeedforward class-AB control. 8 V. Also in CMOS, the circuit with two translinear loops, as is shown in Fig. 23, can be used .
In the transition regions of the current-switches the gm varies about 15%. as is shown in Fig. 17 . It should be noted that the offset voltage of rail-to-rail input stages changes 30 ~----r-----r-----~r------------r-----,--,-~VDD ~--~~----~----~~----------~----~----~V~ Fig. 16. Rail-to-rail input stage. The 3-times current mirrors control the gm' when the complementary input stage gradually switches from one input pair to the other. This change of the offset voltage degrades the CMMR in the transition regions.