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Additional resources for Algorithms and parallel VLSI architectures III: proceedings of the International Workshop, Algorithms and Parallel VLSI Architectures III, Leuven, Belgium, August 29-31, 1994
The ceU-level description of systolic block regularised QR filter. In Eggermont et al. , pages 298-306. Proceedings of the IEEE Signal Processing Society Workshop, held October 20-22, 1993, in Veldhoven, The Netherlands.  J. Kadlec, F. M. F. Gaston, and G. W. Irwin. Parallel implementation of restricted parameter tracking. In J. G. McWhirter, editor, Third IMA International Conference on Mathematics in Signal Processing, Mathematics in Signal Processing, University of Warwick, December 15-17 1992.
This is illustrated diagrammatically by shading the "stationary" data. Figure 2 is not an HSFG in the strictest sense of the meaning, due to the fact that the data has to be fed in sequentially thus not making it an "instantaneous input-output processor". Despite this fact, these type of projections are valuable in determining the architecture and cell descriptions of the resulting systolic array. These cell operations depend, not only on the actual function of the HSFG but also, on the chosen projection, which explains why different systolic architectures can be generated from the same HSFG to produce the same overall mode of operation.
Unlike the standard regularization [5, 7], which is not suitable for systolic implementation, the block-regularization reduces the throughput of the systolic algorithm by only 1/2 in the worst case, compared with the exponentially weighted RLS. Other advantages are that the implementation preserves the compactness of the original array and that it directly provides the transversal filter weights. Acknowledgements This research was supported by Research Grant Nr. 102/93/0897 of the Grant Agency of the Czech Republic.